The Effect of BEOL Design Factors on the Thermal Reliability of Flip-Chip Chip-Scale Packaging
With the development of high-density integrated chips, low-k dielectric materials are used in the back end of line (BEOL) to reduce signal delay.However, due to the application of fine-pitch packages with high-hardness copper pillars, BEOL is susceptible to chip package interaction (CPI), which leads to reliability issues such as the delamination o